View R5F21355DNFP_3666466.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rej03b0286-0100 rev.1.00 page 1 of 43 mar 26, 2010 r8c/35d group renesas mcu datasheet 1. overview 1.1 features the r8c/35d group of single-chip mcus incorporates the r8c cpu core, employing sophisticated instructions for a high level of efficiency. with 1 mbyte of address sp ace, and it is capable of executing instructions at high speed. in addition, the cpu core boasts a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional powe r control. these mcus are designed to maximize emi/ems performance. integration of many peripheral functions, including multif unction timer and serial interface, reduces the number of system components. 1.1.1 applications electronic household appliances, office equipmen t, audio equipment, co nsumer equipment, etc. rej03b0286-0100 rev.1.00 mar 26, 2010
r8c/35d group 1. overview rej03b0286-0100 rev.1.00 page 2 of 43 mar 26, 2010 1.1.2 specifications tables 1.1 and 1.2 outline the specifications for r8c/35d group. table 1.1 specification s for r8c/35d group (1) item function specification cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 1.8 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip m ode (address space: 1 mbyte) memory rom, ram refer to table 1.3 product list for r8c/35d group . power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) i/o ports programmable i/o ports ? input-only: 1 pin ? cmos i/o ports: 47, selectable pull-up resistor ? high current drive ports: 47 clock clock generation circuits ? 4 circuits: xin clock oscillation circuit, xcin clock oscillation circuit (32 khz), high-speed on-chip oscillator (with frequency adjustment function), low-speed on-chip oscillator ? oscillation stop detection: xin cl ock oscillation stop detection function ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (high-speed clock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode real-time clock (timer re) interrupts ? number of interrupt vectors: 69 ? external interrupt: 9 (int 5, key input 4) ? priority levels: 7 levels watchdog timer ? 14 bits 1 (with prescaler) ? reset start selectable ? low-speed on-chip oscillator for watchdog timer selectable timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmabl e waveform generation mode (pwm output), programmable one-shot gen eration mode, programmable wait one- shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 3 pins), pwm2 mode (pwm output pin) timer re 8 bits 1 real-time clock mode (count seconds, mi nutes, hours, days of week), output compare mode serial interface uart0 clock synchronous serial i/o/uart uart2 clock synchronous serial i/o/uart, i 2 c mode (i 2 c-bus), multiprocessor communication function a/d converter 10-bit resolution 12 channels, includes sample and hold function, with sweep mode comparator b 2 circuits
r8c/35d group 1. overview rej03b0286-0100 rev.1.00 page 3 of 43 mar 26, 2010 note: 1. specify the d version if d version functions are to be used. table 1.2 specification s for r8c/35d group (2) item function specification flash memory ? programming and eras ure voltage: vcc = 2.7 to 5.5 v ? programming and erasure endurance: 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function operating frequency/supply voltage f(xin) = 20 mhz (vcc = 2.7 to 5.5 v) f(xin) = 5 mhz (vcc = 1.8 to 5.5 v) current consumption typ. 6.5 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 3.5 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 3.5 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz)) typ. 2.0 a (vcc = 3.0 v, stop mode) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (1) package 52-pin lqfp package code: plqp0052ja-a (previous code: 52p6a-a)
r8c/35d group 1. overview rej03b0286-0100 rev.1.00 page 4 of 43 mar 26, 2010 1.2 product list table 1.3 lists product list for r8c/35d group, and figure 1.1 shows a part number, memory size, and package of r8c/35d group. (d): under development figure 1.1 part number, memory size, and package of r8c/35d group table 1.3 product list for r8c/35d group current of mar. 2010 part no. rom capacity ram capacity package type remarks r5f21354dnfp 16 kbytes 1 kbyte plqp0052ja-a n version R5F21355DNFP 24 kbytes 1 kbyte plqp0052ja-a r5f21356dnfp 32 kbytes 1 kbyte plqp0052ja-a r5f21354ddfp (d) 16 kbytes 1 kbyte plqp0052ja-a d version r5f21355ddfp (d) 24 kbytes 1 kbyte plqp0052ja-a r5f21356ddfp (d) 32 kbytes 1 kbyte plqp0052ja-a part no. r 5 f 21 35 6 d n fp package type: fp: plqp0052ja-a (0.65 mm pin-pitch, 10 mm square body) classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c rom capacity 4: 16 kb 5: 24 kb 6: 32 kb r8c/35d group r8c/3x series memory type f: flash memory renesas mcu renesas semiconductor
r8c/35d group 1. overview rej03b0286-0100 rev.1.00 page 5 of 43 mar 26, 2010 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram r8c cpu core system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout memory rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. 8 port p1 8 port p3 5 1 port p4 8 port p0 8 port p2 2 port p5 timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer re (8 bits 1) uart or clock synchronous serial i/o (8 bits 2) peripheral functions watchdog timer (14 bits) a/d converter (10 bits 12 channels) voltage detection circuit comparator b 8 port p6 low-speed on-chip oscillator for watchdog timer
r8c/35d group 1. overview rej03b0286-0100 rev.1.00 page 6 of 43 mar 26, 2010 1.4 pin assignment figure 1.3 shows the pin assignment (top view). tables 1.4 and 1.5 outline the pin name information by pin number. figure 1.3 pin assignment (top view) 27 39 38 37 36 35 34 33 32 26 14 15 16 17 18 19 20 21 22 23 24 25 1 345678910111213 2 52 51 50 49 48 47 46 45 44 43 42 41 40 p5_7 p6_0(/treo) p6_1 p6_2 p6_3 p6_4 p0_0/an7(/trcioa/trctrg) p0_1/an6(/trcioa/trctrg) p0_2/an5(/trcioa/trctrg) p0_3/an4(/trciob) p0_5/an2(/trciob) p0_6/an1(/trciod) p0_4/an3/treo(/trciob) p2_7 p2_6 p2_5 p2_4 p2_3 p2_2(/trciod) p2_1(/trcioc) p2_0(/int1/trciob) p3_6(/int1) p3_1(/trbo) p0_7/an0(/trcioc) p6_7(/int3/trciod) p6_6/int2(/txd2/sda2/trcioc) p6_5/int4(/clk2/trciob) p4_5/adtrg/int0(/rxd2/scl2) p1_7/ivcmp1/int1(/traio) p1_6/ivref1(/clk0) p1_5(/int1/rxd0/traio) p1_3/an11/kl3/trbo(/trcioc) p1_2/an10/kl2(/trciob) p1_0/an8/ki0(/trciod) p1_1/an9/ki1(/trcioa/trctrg) p1_4(/txd0/trcclk) p5_6(/trao) p3_7/trao(/rxd2/scl2/txd2/sda2) vcc/avcc p4_6/xin vss/avss reset p4_4(/xcout) p3_2(/int1/int2/traio) p4_3(/xcin) p4_7/xout notes: 1. can be assigned to the pin in parentheses by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. 31 30 29 28 p3_5(/clk2/trciod) p3_4/ivref3(/rxd2/scl2/txd2/sda2/trcioc) p3_3/ivcmp3/int3(/cts2/rts2/trcclk) p3_0(/trao) p4_2/vref mode r8c/35d group plqp0052ja-a(52p6a-a) (top view)
r8c/35d group 1. overview rej03b0286-0100 rev.1.00 page 7 of 43 mar 26, 2010 note: 1. can be assigned to the pin in parentheses by a program. table 1.4 pin name informa tion by pin number (1) pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface a/d converter, comparator b 1p5_6(trao) 2p3_2 (int1 /int2 ) (traio) 3p3_0(trao) 4p4_2 vref 5mode 6(xcin)p4_3 7 (xcout) p4_4 8 reset 9xoutp4_7 10 vss/avss 11 xin p4_6 12 vcc/avcc 13 p3_7 trao (rxd2/scl2/ txd2/sda2) 14 p3_5 (trciod) (clk2) 15 p3_4 (trcioc) (rxd2/scl2/ txd2/sda2) ivref3 16 p3_3 int3 (trcclk) (cts2 /rts2 ) ivcmp3 17 p2_7 18 p2_6 19 p2_5 20 p2_4 21 p2_3 22 p2_2 (trciod) 23 p2_1 (trcioc) 24 p2_0 (int1 ) (trciob) 25 p3_6 (int1 ) 26 p3_1 (trbo) 27 p6_7 (int3 ) (trciod) 28 p6_6 int2 (trcioc) (txd2/sda2) 29 p6_5 int4 (trciob) (clk2) 30 p4_5 int0 (rxd2/scl2) adtrg 31 p1_7 int1 (traio) ivcmp1 32 p1_6 (clk0) ivref1 33 p1_5 (int1 ) (traio) (rxd0) 34 p1_4 (trcclk) (txd0) 35 p1_3 ki3 trbo(/trcioc) an11 36 p1_2 ki2 (trciob) an10 37 p1_1 ki1 (trcioa/trctrg) an9 38 p1_0 ki0 (trciod) an8 39 p0_7 (trcioc) an0 40 p0_6 (trciod) an1
r8c/35d group 1. overview rej03b0286-0100 rev.1.00 page 8 of 43 mar 26, 2010 note: 1. can be assigned to the pin in parentheses by a program. table 1.5 pin name informa tion by pin number (2) pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface a/d converter, comparator b 41 p0_5 (trciob) an2 42 p0_4 treo(/trciob) an3 43 p0_3 (trciob) an4 44 p0_2 (trcioa/trctrg) an5 45 p0_1 (trcioa/trctrg) an6 46 p0_0 (trcioa/trctrg) an7 47 p6_4 48 p6_3 49 p6_2 50 p6_1 51 p6_0 (treo) 52 p5_7
r8c/35d group 1. overview rej03b0286-0100 rev.1.00 page 9 of 43 mar 26, 2010 1.5 pin functions table 1.6 lists pin functions. i: input o: output i/o: input and output note: 1. refer to the oscillator manufacturer for oscillation characteristics. table 1.6 pin functions item pin name i/o type description power supply input vcc, vss ? appl y 1.8 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provid ed for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins (1) . to use an external clock, input it to the xout pin and leave the xin pin open. xin clock output xout i/o xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins (1) . to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 to int4 iint interrupt input pins. int0 is timer rb and rc input pin. key input interrupt ki0 to ki3 i key input interrupt input pins timer ra traio i/o timer ra i/o pin trao o timer ra output pin timer rb trbo o timer rb output pin timer rc trcclk i external clock input pin trctrg i external trigger input pin trcioa, trciob, trcioc, trciod i/o timer rc i/o pins timer re treo o divided clock output pin serial interface clk0, clk2 i/o transfer clock i/o pins rxd0, rxd2 i serial data input pins txd0, txd2 o serial data output pins cts2 i transmission control input pin rts2 o reception control output pin scl2 i/o i 2 c mode clock i/o pin sda2 i/o i 2 c mode data i/o pin reference voltage input vref i reference voltage input pin to a/d converter a/d converter an0 to an11 i analog input pins to a/d converter adtrg i a/d external trigger input pin comparator b ivcmp1, ivcmp3 i comparator b analog voltage input pins ivref1, ivref3 i comparator b reference voltage input pins i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_3 to p4_7, p5_6, p5_7, p6_0 to p6_7 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. all ports can be used as led drive ports. input port p4_2 i input-only port
r8c/35d group 2. central processing unit (cpu) rej03b0286-0100 rev.1.00 page 10 of 43 mar 26, 2010 2. central processing unit (cpu) figure 2.1 shows the cpu registers. th e cpu contains 13 registers. r0, r1 , r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1)
r8c/35d group 2. central processing unit (cpu) rej03b0286-0100 rev.1.00 page 11 of 43 mar 26, 2010 2.1 data registers (r0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address regist ers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is an alogous to a0. a1 can be combined with a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the starting address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) the stack pointers (sp), usp and is p, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operati on results in an overflow; otherwise to 0.
r8c/35d group 2. central processing unit (cpu) rej03b0286-0100 rev.1.00 page 12 of 43 mar 26, 2010 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0, and are enabled when th e i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt reque st is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interr upt priority levels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined.
r8c/35d group 3. memory rej03b0286-0100 rev.1.00 page 13 of 43 mar 26, 2010 3. memory 3.1 r8c/35d group figure 3.1 is a memory map of r8c/35d group. the r8 c/35d group has a 1-mbyte address space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower ad dresses, beginning with address 0ffffh. for example, a 32-kbyte internal rom area is allocated addresses 08000h to 0ffffh. the fixed interrupt vector table is allocated addresses 0ffdch to 0ffffh. the starting address of each interrupt routine is stored here. the internal ram is allocated higher addresses, beginni ng with address 00400h. for example, a 1-kbyte internal ram area is allocated addresses 00400h to 007ffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. special function registers (sfrs) are allocated addres ses 00000h to 002ffh. peripheral function control registers are allocated here. all unallocated spaces within th e sfrs are reserved and cannot be accessed by users. figure 3.1 memory map of r8c/35d group part number r5f21354dnfp, r5f21354ddfp R5F21355DNFP, r5f21355ddfp r5f21356dnfp, r5f21356ddfp internal rom internal ram size address 0yyyyh size address 0xxxxh 16 kbytes 24 kbytes 32 kbytes 0c000h 0a000h 08000h 1 kbyte 1 kbyte 1 kbyte 007ffh 007ffh 007ffh 0ffffh 0ffdch note: 1. the blank areas are reserved and cannot be accessed by users. fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffd8h reserved area undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor (reserved) (reserved) reset
r8c/35d group 4. special function registers (sfrs) rej03b0286-0100 rev.1.00 page 14 of 43 mar 26, 2010 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.8 list the special function registers and table 4.9 lists the id code areas and option function select area. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank areas are reserved and cannot be accessed by users. 2. the cwr bit in the rstfr register is set to 0 after power-on and voltage monitor 0 reset. hardware reset, software reset, or watchdog timer reset does not affect this bit. 3. the csproini bit in the ofs register is set to 0. 4. the lvdas bit in the ofs register is set to 1. 5. the lvdas bit in the ofs register is set to 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 00101000b 0007h system clock control register 1 cm1 00100000b 0008h module standby control register mstcr 00h 0009h system clock control register 3 cm3 00h 000ah protect register prcr 00h 000bh reset source determination register rstfr 0xxxxxxxb (2) 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdtc 00111111b 0010h 0011h 0012h 0013h 0014h 0015h high-speed on-chip oscillator control register 7 fra7 when shipping 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (3) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h on-chip reference voltage control register ocvrefcr 00h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h high-speed on-chip oscillator control register 4 fra4 when shipping 002ah high-speed on-chip oscillator control register 5 fra5 when shipping 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch 002dh 002eh 002fh high-speed on-chip oscillator control register 3 fra3 when shipping 0030h voltage monitor circuit control register cmpa 00h 0031h voltage monitor circuit edge select register vcac 00h 0032h 0033h voltage detect register 1 vca1 00001000b 0034h voltage detect register 2 vca2 00h (4) 00100000b (5) 0035h 0036h voltage detection 1 level select register vd1ls 00000111b 0037h 0038h voltage monitor 0 circuit control register vw0c 1100x010b (4) 1100x011b (5) 0039h voltage monitor 1 circuit control register vw1c 10001010b
r8c/35d group 4. special function registers (sfrs) rej03b0286-0100 rev.1.00 page 15 of 43 mar 26, 2010 table 4.2 sfr information (2) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 003ah voltage monitor 2 circuit control register vw2c 10000010b 003bh 003ch 003dh 003eh 003fh 0040h 0041h flash memory ready interrupt control register fmrdyic xxxxx000b 0042h 0043h 0044h 0045h 0046h int4 interrupt control register int4ic xx00x000b 0047h timer rc interrupt control register trcic xxxxx000b 0048h 0049h 004ah timer re interrupt control register treic xxxxx000b 004bh uart2 transmit interrupt control register s2tic xxxxx000b 004ch uart2 receive interrupt control register s2ric xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h 0054h 0055h int2 interrupt control register int2ic xx00x000b 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh uart2 bus collision detection interrupt control register u2bcnic xxxxx000b 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h voltage monitor 1 interrupt control register vcmp1ic xxxxx000b 0073h voltage monitor 2 interrupt control register vcmp2ic xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh
r8c/35d group 4. special function registers (sfrs) rej03b0286-0100 rev.1.00 page 16 of 43 mar 26, 2010 table 4.3 sfr information (3) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart2 transmit/receive mode register u2mr 00h 00a9h uart2 bit rate register u2brg xxh 00aah uart2 transmit buffer register u2tb xxh 00abh xxh 00ach uart2 transmit/receive control register 0 u2c0 00001000b 00adh uart2 transmit/receive control register 1 u2c1 00000010b 00aeh uart2 receive buffer register u2rb xxh 00afh xxh 00b0h uart2 digital filter function select register urxdf 00h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh uart2 special mode register 5 u2smr5 00h 00bch uart2 special mode register 4 u2smr4 00h 00bdh uart2 special mode register 3 u2smr3 000x0x0xb 00beh uart2 special mode register 2 u2smr2 x0000000b 00bfh uart2 special mode register u2smr x0000000b
r8c/35d group 4. special function registers (sfrs) rej03b0286-0100 rev.1.00 page 17 of 43 mar 26, 2010 table 4.4 sfr information (4) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 00c0h a/d register 0 ad0 xxh 000000xxb 00c1h 00c2h a/d register 1 ad1 xxh 00c3h 000000xxb 00c4h a/d register 2 ad2 xxh 00c5h 000000xxb 00c6h a/d register 3 ad3 xxh 00c7h 000000xxb 00c8h a/d register 4 ad4 xxh 00c9h 000000xxb 00cah a/d register 5 ad5 xxh 00cbh 000000xxb 00cch a/d register 6 ad6 xxh 00cdh 000000xxb 00ceh a/d register 7 ad7 xxh 00cfh 000000xxb 00d0h 00d1h 00d2h 00d3h 00d4h a/d mode register admod 00h 00d5h a/d input select register adinsel 11000000b 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h port p5 register p5 xxh 00eah port p4 direction register pd4 00h 00ebh port p5 direction register pd5 00h 00ech port p6 register p6 xxh 00edh 00eeh port p6 direction register pd6 00h 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh
r8c/35d group 4. special function registers (sfrs) rej03b0286-0100 rev.1.00 page 18 of 43 mar 26, 2010 table 4.5 sfr information (5) (1) note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h 0106h 0107h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register trehr 00h 011bh timer re day of week data register trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re count source select register trecsr 00001000b 011fh 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 0127h 00h 0128h timer rc general register a trcgra ffh 0129h ffh 012ah timer rc general register b trcgrb ffh 012bh ffh 012ch timer rc general register c trcgrc ffh 012dh ffh 012eh timer rc general register d trcgrd ffh 012fh ffh 0130h timer rc control register 2 trccr2 00011000b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 0 1111111b 0133h timer rc trigger control register trcadcr 00h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh
r8c/35d group 4. special function registers (sfrs) rej03b0286-0100 rev.1.00 page 19 of 43 mar 26, 2010 table 4.6 sfr information (6) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh
r8c/35d group 4. special function registers (sfrs) rej03b0286-0100 rev.1.00 page 20 of 43 mar 26, 2010 table 4.7 sfr information (7) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 0180h timer ra pin select register trasr 00h 0181h timer rb/rc pin select register trbrcsr 00h 0182h timer rc pin select register 0 trcpsr0 00h 0183h timer rc pin select register 1 trcpsr1 00h 0184h 0185h 0186h timer pin select register timsr 00h 0187h 0188h uart0 pin select register u0sr 00h 0189h 018ah uart2 pin select register 0 u2sr0 00h 018bh uart2 pin select register 1 u2sr1 00h 018ch 018dh 018eh int interrupt input pin select register intsr 00h 018fh i/o function pin select register pinsr 00h 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h flash memory status register fst 10000x00b 01b3h 01b4h flash memory control register 0 fmr0 00h 01b5h flash memory control register 1 fmr1 00h 01b6h flash memory control register 2 fmr2 00h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh
r8c/35d group 4. special function registers (sfrs) rej03b0286-0100 rev.1.00 page 21 of 43 mar 26, 2010 table 4.8 sfr information (8) (1) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 01c0h address match interrupt register 0 rmad0 xxh 01c1h xxh 01c2h 0000xxxxb 01c3h address match interrupt enable register aier 00h 01c4h address match interrupt register 1 rmad1 xxh 01c5h xxh 01c6h 0000xxxxb 01c7h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h pull-up control register 0 pur0 00h 01e1h pull-up control register 1 pur1 00h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h port p1 drive capacity control register p1drr 00h 01f1h port p2 drive capacity control register p2drr 00h 01f2h drive capacity control register 0 drr0 00h 01f3h drive capacity control register 1 drr1 00h 01f4h 01f5h input threshold control register 0 vlt0 00h 01f6h input threshold control register 1 vlt1 00h 01f7h 01f8h comparator b control register 0 intcmp 00h 01f9h 01fah external input enable register 0 inten 00h 01fbh external input enable register 1 inten1 00h 01fch int input filter select register 0 intf 00h 01fdh int input filter select register 1 intf1 00h 01feh key input enable register 0 kien 00h 01ffh
r8c/35d group 4. special function registers (sfrs) rej03b0286-0100 rev.1.00 page 22 of 43 mar 26, 2010 table 4.9 id code areas and option function select area notes: 1. the option function select area is allocated in the flash memory , not in the sfrs. set appropriate values as rom data by a pr ogram. do not write additions to the option function select area. if the block including the option function select area is erased, th e option function select area is set to ffh. when blank products are shipped, the option function select area is set to ffh. it is set to the written value after written by the user. when factory-programming products are shipped, the value of the option function select area is the value programmed by the user . 2. the id code areas are allocated in the flash memory, not in the sfrs. set appropriate values as rom data by a program. do not write additions to the id code areas. if the block includ ing the id code areas is erased, the id code areas are set to f fh. when blank products are shipped, the id code areas are set to ffh. they are set to the written value after written by the user. when factory-programming products are shipped, the value of the id code areas is the value programmed by the user. address area name symbol after reset : ffdbh option function select register 2 ofs2 (note 1) : ffdfh id1 (note 2) : ffe3h id2 (note 2) : ffebh id3 (note 2) : ffefh id4 (note 2) : fff3h id5 (note 2) : fff7h id6 (note 2) : fffbh id7 (note 2) : ffffh option function select register ofs (note 1)
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 23 of 43 mar 26, 2010 5. electrical characteristics table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage ? 0.3 to 6.5 v v i input voltage ? 0.3 to v cc + 0.3 v v o output voltage ? 0.3 to v cc + 0.3 v p d power dissipation ? 40 c t opr 85 c 500 mw t opr operating ambient temperature ? 20 to 85 (n version) / ? 40 to 85 (d version) c t stg storage temperature ? 65 to 150 c
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 24 of 43 mar 26, 2010 notes: 1. v cc = 1.8 to 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. the average output current indicates the av erage value of current measured during 100 ms. 3. foco40m can be used as the count s ource for timer rc in the range of v cc = 2.7 to 5.5 v. table 5.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 1.8 ? 5.5 v v ss /av ss supply voltage ?0?v v ih input ?h? voltage other than cmos input 0.8 v cc ?v cc v cmos input input level switching function (i/o port) input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0.5 v cc ?v cc v 2.7 v v cc < 4.0 v 0.55 v cc ?v cc v 1.8 v v cc < 2.7 v 0.65 v cc ?v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0.65 v cc ?v cc v 2.7 v v cc < 4.0 v 0.7 v cc ?v cc v 1.8 v v cc < 2.7 v 0.8 v cc ?v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0.85 v cc ?v cc v 2.7 v v cc < 4.0 v 0.85 v cc ?v cc v 1.8 v v cc < 2.7 v 0.85 v cc ?v cc v external clock input (xout) 1.2 ? v cc v v il input ?l? voltage other than cmos input 0 ? 0.2 v cc v cmos input input level switching function (i/o port) input level selection : 0.35 v cc 4.0 v v cc 5.5 v 0 ? 0.2 v cc v 2.7 v v cc < 4.0 v 0 ? 0.2 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.5 v cc 4.0 v v cc 5.5 v 0 ? 0.4 v cc v 2.7 v v cc < 4.0 v 0 ? 0.3 v cc v 1.8 v v cc < 2.7 v 0 ? 0.2 v cc v input level selection : 0.7 v cc 4.0 v v cc 5.5 v 0 ? 0.55 v cc v 2.7 v v cc < 4.0 v 0 ? 0.45 v cc v 1.8 v v cc < 2.7 v 0 ? 0.35 v cc v external clock input (xout) 0 ? 0.4 v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? ? 160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? ? 80 ma i oh(peak) peak output ?h? current drive capacity low ? ? ? 10 ma drive capacity high ? ? ? 40 ma i oh(avg) average output ?h? current drive capacity low ? ? ? 5ma drive capacity high ? ? ? 20 ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ??160ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ??80ma i ol(peak) peak output ?l? current drive capacity low ? ? 10 ma drive capacity high ? ? 40 ma i ol(avg) average output ?l? current drive capacity low ? ? 5 ma drive capacity high ? ? 20 ma f (xin) xin clock input oscill ation frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz f (xcin) xcin clock input oscillation frequency 1.8 v v cc 5.5 v ? 32.768 50 khz foco40m when used as the count source for timer rc (3) 2.7 v v cc 5.5 v 32 ? 40 mhz foco-f foco-f frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz ? system clock frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz f (bclk) cpu clock frequency 2.7 v v cc 5.5 v ? ? 20 mhz 1.8 v v cc < 2.7 v ? ? 5 mhz
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 25 of 43 mar 26, 2010 figure 5.1 ports p0 to p6 timing measurement circuit p0 p1 p2 p3 p4 p5 p6 30 pf
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 26 of 43 mar 26, 2010 notes: 1. v cc /av cc = v ref = 2.2 to 5.5 v, v ss = 0 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. the a/d conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-current- consumption mode. do not perform a/d conversion in these states or transition to these states during a/d conversion. 3. when the analog input voltage is over the reference voltage, the a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. notes: 1. v cc = 2.7 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. when the digital filter is disabled. table 5.3 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ??10bit ? absolute accuracy 10-bit mode v ref = av cc = 5.0 v an0 to an7 input, an8 to an11 input ??3lsb v ref = av cc = 3.3 v an0 to an7 input, an8 to an11 input ??5lsb v ref = av cc = 3.0 v an0 to an7 input, an8 to an11 input ??5lsb v ref = av cc = 2.2 v an0 to an7 input, an8 to an11 input ??5lsb 8-bit mode v ref = av cc = 5.0 v an0 to an7 input, an8 to an11 input ??2lsb v ref = av cc = 3.3 v an0 to an7 input, an8 to an11 input ??2lsb v ref = av cc = 3.0 v an0 to an7 input, an8 to an11 input ??2lsb v ref = av cc = 2.2 v an0 to an7 input, an8 to an11 input ??2lsb ad a/d conversion clock 4.0 v v ref = av cc 5.5 v (2) 2?20mhz 3.2 v v ref = av cc 5.5 v (2) 2?16mhz 2.7 v v ref = av cc 5.5 v (2) 2?10mhz 2.2 v v ref = av cc 5.5 v (2) 2?5mhz ? tolerance level impedance ? 3 ? k ? t conv conversion time 10-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.15 ? ? s 8-bit mode v ref = av cc = 5.0 v, ad = 20 mhz 2.15 ? ? s t samp sampling time ad = 20 mhz 0.75 ? ? s i vref v ref current v cc = 5.0 v, xin = f1 = ad = 20 mhz ? 45 ? a v ref reference voltage 2.2 ? av cc v v ia analog input voltage (3) 0?v ref v ocvref on-chip reference voltage 2 mhz ad 4 mhz 1.19 1.34 1.49 v table 5.4 comparator b electrical characteristics symbol parameter condition standard unit min. typ. max. vref ivref1, ivref3 input reference voltage 0 ? v cc ? 1.4 v v i ivcmp1, ivcmp3 input voltage ? 0.3 ? v cc + 0.3 v ? offset ? 5 100 mv t d comparator output delay time (2) v i = vref 100 mv ? 0.1 ? s i cmp comparator operating current v cc = 5.0 v ? 17.5 ? a
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 27 of 43 mar 26, 2010 notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 1,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to different addresses in block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics afte r program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, a ttempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the po wer supply is off or the clock is not supplied. figure 5.2 time delay until suspend table 5.5 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 1,000 (3) ??times ? byte program time ? 80 500 s ? block erase time ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ? ? 5 + cpu clock 3 cycles ms ? interval from erase start/restart until following suspend request 0? ? s ? time from suspend until erase restart ? ? 30 + cpu clock 1 cycle s t d(cmdrst- ready) time from when command is forcibly stopped until reading is enabled ? ? 30 + cpu clock 1 cycle s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 1.8 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c 20 ? ? year fst6 bit suspend request (fmr21 bit) fixed time clock-dependent time access restart fst6, fst7: bits in fst register fmr21: bit in fmr2 register fst7 bit t d(sr-sus)
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 28 of 43 mar 26, 2010 notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. select the voltage detection level with bits vdsel0 and vdsel1 in the ofs register. 3. necessary time until the voltage detecti on circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. 4. time until the voltage monitor 0 reset is generated after the voltage passes v det0 . notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. select the voltage detection level with bits vd1s0 to vd1s3 in the vd1ls register. 3. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 4. necessary time until the voltage detecti on circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. table 5.6 voltage detection 0 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level vdet0_0 (2) 1.80 1.90 2.05 v voltage detection level vdet0_1 (2) 2.15 2.35 2.50 v voltage detection level vdet0_2 (2) 2.70 2.85 3.05 v voltage detection level vdet0_3 (2) 3.55 3.80 4.05 v ? voltage detection 0 circuit response time (4) at the falling of v cc from 5 v to (vdet0_0 ? 0.1) v ? 6 150 s ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 1.5 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s table 5.7 voltage detection 1 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level vdet1_0 (2) at the falling of v cc 2.00 2.20 2.40 v voltage detection level vdet1_1 (2) at the falling of v cc 2.15 2.35 2.55 v voltage detection level vdet1_2 (2) at the falling of v cc 2.30 2.50 2.70 v voltage detection level vdet1_3 (2) at the falling of v cc 2.45 2.65 2.85 v voltage detection level vdet1_4 (2) at the falling of v cc 2.60 2.80 3.00 v voltage detection level vdet1_5 (2) at the falling of v cc 2.75 2.95 3.15 v voltage detection level vdet1_6 (2) at the falling of v cc 2.85 3.10 3.40 v voltage detection level vdet1_7 (2) at the falling of v cc 3.00 3.25 3.55 v voltage detection level vdet1_8 (2) at the falling of v cc 3.15 3.40 3.70 v voltage detection level vdet1_9 (2) at the falling of v cc 3.30 3.55 3.85 v voltage detection level vdet1_a (2) at the falling of v cc 3.45 3.70 4.00 v voltage detection level vdet1_b (2) at the falling of v cc 3.60 3.85 4.15 v voltage detection level vdet1_c (2) at the falling of v cc 3.75 4.00 4.30 v voltage detection level vdet1_d (2) at the falling of v cc 3.90 4.15 4.45 v voltage detection level vdet1_e (2) at the falling of v cc 4.05 4.30 4.60 v voltage detection level vdet1_f (2) at the falling of v cc 4.20 4.45 4.75 v ? hysteresis width at the rising of v cc in voltage detection 1 circuit vdet1_0 to vdet1_5 selected ?0.07? v vdet1_6 to vdet1_f selected ?0.10? v ? voltage detection 1 circuit response time (3) at the falling of v cc from 5 v to (vdet1_0 ? 0.1) v ? 60 150 s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (4) ? ? 100 s
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 29 of 43 mar 26, 2010 notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates af ter setting to 1 again after setting the vca27 bit in the vca2 register to 0. notes: 1. the measurement condition is t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. to use the power-on reset function, enable voltage monitor 0 reset by setting the lvdas bit in the ofs register to 0. figure 5.3 power-on reset circuit electrical characteristics table 5.8 voltage detection 2 circ uit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level vdet2_0 at the falling of v cc 3.70 4.00 4.30 v ? hysteresis width at the rising of v cc in voltage detection 2 circuit ?0.10? v ? voltage detection 2 circuit response time (2) at the falling of v cc from 5 v to (vdet2_0 ? 0.1) v ? 20 150 s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 1.7 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ? ? 100 s table 5.9 power-on reset circuit (2) symbol parameter condition standard unit min. typ. max. t rth external power v cc rise gradient (1) 0 ? 50000 mv/msec notes: 1. v det0 indicates the voltage detection level of the voltage detection 0 circuit. 2. t w(por) indicates the duration the external power v cc must be held below the valid voltage (0.5 v) to enable a power-on reset. when turning on the power after it falls with voltage monitor 0 reset disabled, maintain t w(por) for 1 ms or more. v det0 (1) 0.5 v internal reset signal t w(por) (2) voltage detection 0 circuit response time v det0 (1) 1 f oco-s 32 1 f oco-s 32 external power v cc t rth t rth
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 30 of 43 mar 26, 2010 notes: 1. v cc = 1.8 v to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. 2. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. v cc = 1.8 to 5.5 v, t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 1.8 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power suppl y generation circuit stabilizes during power-on. table 5.10 high-speed on-chi p oscillator circuit el ectrical characteristics symbol parameter condition standard unit min. typ. max. ? high-speed on-chip oscillator frequency after reset v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 38.4 40 41.6 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 38.0 40 42.0 mhz high-speed on-chip oscillator frequency when the fra4 register correction value is written into the fra1 register and the fra5 register correction value into the fra3 register (2) v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 35.389 36.864 38.338 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 35.020 36.864 38.707 mhz high-speed on-chip oscillator frequency when the fra6 register correction value is written into the fra1 register and the fra7 register correction value into the fra3 register v cc = 1.8 v to 5.5 v ? 20 c t opr 85 c 30.72 32 33.28 mhz v cc = 1.8 v to 5.5 v ? 40 c t opr 85 c 30.40 32 33.60 mhz ? oscillation stability time v cc = 5.0 v, t opr = 25 c?0.53ms ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c?400? a table 5.11 low-speed on-chi p oscillator circuit el ectrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 60 125 250 khz ? oscillation stability time v cc = 5.0 v, t opr = 25 c ? 30 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c? 2 ? a table 5.12 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) ? ? 2000 s
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 31 of 43 mar 26, 2010 note: 1. 4.2 v v cc 5.5 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 20 mhz, unless otherwise specified. table 5.13 electrical characteristics (1) [4.2 v v cc 5.5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage other than xout drive capacity high v cc = 5 v i oh = ? 20 ma v cc ? 2.0 ? v cc v drive capacity low v cc = 5 v i oh = ? 5 ma v cc ? 2.0 ? v cc v xout v cc = 5 v i oh = ? 200 a1.0 ?v cc v v ol output ?l? voltage other than xout drive capacity high v cc = 5 v i ol = 20 ma ? ? 2.0 v drive capacity low v cc = 5 v i ol = 5 ma ? ? 2.0 v xout v cc = 5 v i ol = 200 a? ?0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , ki0 , ki1 , ki2 , ki3 , traio, trbo, trcioa, trciob, trcioc, trciod, trctrg, trcclk, adtrg , rxd0, rxd2, clk0, clk2 0.1 1.2 ? v reset 0.1 1.2 ? v i ih input ?h? current v i = 5 v, v cc = 5.0 v ? ? 5.0 a i il input ?l? current v i = 0 v, v cc = 5.0 v ? ? ? 5.0 a r pullup pull-up resistance v i = 0 v, v cc = 5.0 v 25 50 100 k ? r fxin feedback resistance xin ?0.3?m ? r fxcin feedback resistance xcin ? 8 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 32 of 43 mar 26, 2010 table 5.14 electrical characteristics (2) [3.3 v v cc 5.5 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?6.515ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 5.3 12.5 ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?3.6?ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?3.0?ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?2.2?ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.5?ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz no division ?7.015ma xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?3.0?ma xin clock off high-speed on-chip oscillator on foco-f = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-16 msttrc = 1 ?1?ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 0 ? 90 400 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division fmr27 = 1, vca20 = 0 ? 85 400 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division program operation on ram flash memory off, fmstp = 1, vca20 = 0 ?47? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 15 100 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ?490 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (peripheral clock off) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ?3.5? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?2.05.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?5.0? a
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 33 of 43 mar 26, 2010 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at t opr = 25 c) figure 5.4 external clock input timing diagram when v cc = 5 v figure 5.5 traio input timing diagram when v cc = 5 v table 5.15 external clock input (xout, xcin) symbol parameter standard unit min. max. t c(xout) xout input cycle time 50 ? ns t wh(xout) xout input ?h? width 24 ? ns t wl(xout) xout input ?l? width 24 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.16 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns v cc = 5 v external clock input t wh(xout), t wh(xcin) t c(xout), t c(xcin) t wl(xout), t wl(xcin) traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio)
r8c/35d group 5. electr ical characteristics rej03b0286-0100 rev.1.00 page 34 of 43 mar 26, 2010 i = 0, 2 figure 5.6 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.7 input timing for external interrupt int i and key input interrupt kii when v cc = 5 v table 5.17 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.18 external interrupt inti (i = 0 to 4) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 250 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 250 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0, 2 v cc = 5 v inti input (i = 0 to 4) t w(inl) t w(inh) v cc = 5 v kii input (i = 0 to 3)
r8c/35d group 5. electrical characteristics rej03b0286-0100 rev.1.00 page 35 of 43 mar 26, 2010 note: 1. 2.7 v v cc < 4.2 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 10 mhz, unless otherwise specified. table 5.19 electrical characteristics (3) [2.7 v v cc < 4.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage other than xout drive capacity high i oh = ? 5 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout i oh = ? 200 a1.0 ?v cc v v ol output ?l? voltage other than xout drive capacity high i ol = 5 ma ? ? 0.5 v drive capacity low i ol = 1 ma ? ? 0.5 v xout i ol = 200 a? ?0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , ki0 , ki1 , ki2 , ki3 , traio, trbo, trcioa, trciob, trcioc, trciod, trctrg, trcclk, adtrg , rxd0, rxd2, clk0, clk2 v cc = 3.0 v 0.1 0.4 ? v reset v cc = 3.0 v 0.1 0.5 ? v i ih input ?h? current v i = 3 v, v cc = 3.0 v ? ? 4.0 a i il input ?l? current v i = 0 v, v cc = 3.0 v ? ? ? 4.0 a r pullup pull-up resistance v i = 0 v, v cc = 3.0 v 42 84 168 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 8 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v
r8c/35d group 5. electrical characteristics rej03b0286-0100 rev.1.00 page 36 of 43 mar 26, 2010 table 5.20 electrical characteristics (4) [2.7 v v cc < 3.3 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?3.510ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.57.5ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz no division ?7.015ma xin clock off high-speed on-chip oscillator on foco-f = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?3.0?ma xin clock off high-speed on-chip oscillator on foco-f = 10 mhz low-speed on-chip oscillator on = 125 khz no division ?4.0?ma xin clock off high-speed on-chip oscillator on foco-f = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.5?ma xin clock off high-speed on-chip oscillator on foco-f = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-16 msttrc = 1 ?1?ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 0 ? 90 390 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division fmr27 = 1, vca20 = 0 ? 80 400 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division program operation on ram flash memory off, fmstp = 1, vca20 = 0 ?40? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0, vca20 = 1 ?1590 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0, vca20 = 1 ?480 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (peripheral clock off) while a wait instruction is executed vca27 = vca26 = vca25 = 0, vca20 = 1 ?3.5? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?2.05.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?5.0? a
r8c/35d group 5. electrical characteristics rej03b0286-0100 rev.1.00 page 37 of 43 mar 26, 2010 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at t opr = 25 c) figure 5.8 external clock input timing diagram when v cc = 3 v figure 5.9 traio input timing diagram when v cc = 3 v table 5.21 external clock input (xout, xcin) symbol parameter standard unit min. max. t c(xout) xout input cycle time 50 ? ns t wh(xout) xout input ?h? width 24 ? ns t wl(xout) xout input ?l? width 24 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.22 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns v cc = 3 v external clock input t wh(xout), t wh(xcin) t c(xout), t c(xcin) t wl(xout), t wl(xcin) traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio)
r8c/35d group 5. electrical characteristics rej03b0286-0100 rev.1.00 page 38 of 43 mar 26, 2010 i = 0, 2 figure 5.10 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.11 input timing for external interrupt int i and key input interrupt kii when v cc = 3 v table 5.23 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.24 external interrupt inti (i = 0 to 4) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 380 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 380 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0, 2 t w(inl) t w(inh) v cc = 3 v inti input (i = 0 to 4) kii input (i = 0 to 3)
r8c/35d group 5. electrical characteristics rej03b0286-0100 rev.1.00 page 39 of 43 mar 26, 2010 note: 1. 1.8 v v cc < 2.7 v at t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), f(xin) = 5 mh z, unless otherwise specified. table 5.25 electrical characteristics (5) [1.8 v v cc < 2.7 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage other than xout drive capacity high i oh = ? 2 ma v cc ? 0.5 ? v cc v drive capacity low i oh = ? 1 ma v cc ? 0.5 ? v cc v xout i oh = ? 200 a1.0 ?v cc v v ol output ?l? voltage other than xout drive capacity high i ol = 2 ma ? ? 0.5 v drive capacity low i ol = 1 ma ? ? 0.5 v xout i ol = 200 a? ?0.5v v t+- v t- hysteresis int0 , int1 , int2 , int3 , int4 , ki0 , ki1 , ki2 , ki3 , traio, trbo, trcioa, trciob, trcioc, trciod, trctrg, trcclk, adtrg , rxd0, rxd2, clk0, clk2 0.05 0.20 ? v reset 0.05 0.20 ? v i ih input ?h? current v i = 2.2 v, v cc = 2.2 v ? ? 4.0 a i il input ?l? current v i = 0 v, v cc = 2.2 v ? ? ? 4.0 a r pullup pull-up resistance v i = 0 v, v cc = 2.2 v 70 140 300 k ? r fxin feedback resistance xin ? 0.3 ? m ? r fxcin feedback resistance xcin ? 8 ? m ? v ram ram hold voltage during stop mode 1.8 ? ? v
r8c/35d group 5. electrical characteristics rej03b0286-0100 rev.1.00 page 40 of 43 mar 26, 2010 table 5.26 electrical characteristics (6) [1.8 v v cc < 2.7 v] (t opr = ? 20 to 85 c (n version) / ? 40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 1.8 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ?2.2?ma xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ?0.8?ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco-f = 5 mhz low-speed on-chip oscillator on = 125 khz no division ?2.510ma xin clock off high-speed on-chip oscillator on foco-f = 5 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ?1.7?ma xin clock off high-speed on-chip oscillator on foco-f = 4 mhz low-speed on-chip oscillator on = 125 khz divide-by-16 msttrc = 1 ?1?ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr27 = 1, vca20 = 0 ? 90 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division fmr27 = 1, vca20 = 0 ? 80 350 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz no division program operation on ram flash memory off, fmstp = 1, vca20 = 0 ?40? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ?1590 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ?480 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (peripheral clock off) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ?3.5? a stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?2.05 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ?5.0? a
r8c/35d group 5. electrical characteristics rej03b0286-0100 rev.1.00 page 41 of 43 mar 26, 2010 timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v at t opr = 25 c) figure 5.12 external clock input timing diagram when v cc = 2.2 v figure 5.13 traio input timing diagram when v cc = 2.2 v table 5.27 external clock input (xout, xcin) symbol parameter standard unit min. max. t c(xout) xout input cycle time 200 ? ns t wh(xout) xout input ?h? width 90 ? ns t wl(xout) xout input ?l? width 90 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.28 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns v cc = 2.2 v external clock input t wh(xout), t wh(xcin) t c(xout), t c(xcin) t wl(xout), t wl(xcin) traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v
r8c/35d group 5. electrical characteristics rej03b0286-0100 rev.1.00 page 42 of 43 mar 26, 2010 i = 0, 2 figure 5.14 serial interface timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.15 input timing for external interrupt int i and key input interrupt kii when v cc = 2.2 v table 5.29 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.30 external interrupt inti (i = 0 to 4) input, key input interrupt kii (i = 0 to 3) symbol parameter standard unit min. max. t w(inh) inti input ?h? width, kii input ?h? width 1000 (1) ?ns t w(inl) inti input ?l? width, kii input ?l? width 1000 (2) ?ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0, 2 v cc = 2.2 v t w(inl) t w(inh) inti input (i = 0 to 4) kii input (i = 0 to 3) v cc = 2.2 v
r8c/35d group package dimensions rej03b0286-0100 rev.1.00 page 43 of 43 mar 26, 2010 package dimensions diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas electronics website. include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. detail f c a l1 l a2 a1 index mark x y * 3 * 1 * 2 f 39 27 13 1 40 52 26 14 zd ze d hd e he bp terminal cross section c bp c1 b1 previous code jeita package code renesas code plqp0052ja-a 52p6a-a mass[typ.] 0.3g p-lqfp52-10x10-0.65 1.0 0.125 0.30 1.1 1.1 0.13 0.20 0.145 0.09 0.37 0.32 0.27 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.65 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 e
r8c/35d group datasheet c - 1 rev. date description page summary 0.01 sep 10, 2009 ? first edition issued 1.00 mar 26, 2010 all pages ?preliminary?, ?under development? deleted 4 table 1.3 revised 23 to 42 ?5. electrical characteristics? added all trademarks and registered trademarks are the property of their respective owners. revision history
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is s ubject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose rela ting to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporate d into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", an d "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics produ ct before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. fu rther, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended wh ere you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electroni cs data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or syst ems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct thr eat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas el ectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design . please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compati bility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 7f, no. 363 fu shing north road taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2010 renesas electronics corporation. all rights reserved. colophon 1.0

▲Up To Search▲

Price & Availability of R5F21355DNFP

	To Download R5F21355DNFP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .